Today, semiconductor manufacturing especially of a very large scale integrated circuit (VLSI) that is formed on a silicon substrate, indispensably entails micro fabrication of elements or circuit components and forming multilayer interconnect wiring to bond the elements. As operation at lower voltages and higher processing speed are required for more semiconductor devices, imperative is reducing dielectric constant of the ILD among the multilayer interconnect wiring. Particularly in manufacturing logic integrated circuits (ICs), a problem is decrease of processing speed of ICs caused by increase of resistance and increase of parasitic capacitance as a result of microscopic wiring onto the ILD. A solution is to apply insulating film materials of low dielectric constant to the ILD for multilayer interconnect wiring structure. The low dielectric constant insulating film means here an insulating film of which dielectric constant is less than four (4) which is dielectric constant of silicon dioxide.
Other low dielectric constant insulating films are an insulating film of siloxanes backbone, an insulating film of organic polymer molecule for main chain, and a porous insulating films of these two kinds of materials. Dielectric constant of the insulating films of siloxanes backbone is less than three (3). Those films are a silica film which consists of at least one (1) of Si—CH3 bonding, Si—H bonding, and Si—F bonding as of silsesquioxane insulating films and a film of silicon oxide with carbon (SiOC film).
An example of the insulating film material of organic polymer for main chain is well-known SiLK (registered trademark). Dielectric constant of this type of films is generally lower than that of the insulating films of siloxanes backbone.
Well-known insulating materials for silsesquioxane insulating films are Methyl Silsesquioxane (MSQ), Hydrogen Silsesquioxane (HSQ), and Methylated Hydrogen Silsesquioxane (MHSQ). By making those silsesquioxane insulating films porous, dielectric constant can be easily two (2) to three (3).
Process by use of a mask of resist is essential to apply abovementioned insulating materials of low dielectric constant to an ILD and to form multilayer interconnect wiring onto a substrate. Such processing includes, for example, forming a via (hole) to connect between multilayer interconnects, or forming wiring trench(es) for buried wiring (damascene wiring or dual damascene wiring). Now, explained is outline of the process to make a via onto insulating films of low dielectric constant referring to FIG. 9A-9D in the appended drawings. FIG. 9A-9D depicts a modeling cross section of an ILD with a via in the order of process sequence.
As shown in FIG. 9A, on the surface of a P-conductive (for an instance) silicon substrate 101, an n-conductive diffusion layer 102 is formed; and on the surface of the silicon substrate 101, a silicon oxide film 103 is formed in 50 nm thickness, for instance, by thermal oxidation. Then, on the silicon oxide film 103, a MSQ film 104 about 1.5 μm thick is formed by widely-known spin-on coating method, and laminating on the MSQ film 104, a protection insulating film 105 is made. In this case the protection film 105 is a silicon carbide (SiC) film of 50 nm thickness. Thus, in this case of process, the protection insulating film 105, the MSQ film 104, and the silicon oxide film 103 together constitute the ILD 106. Subsequently, by photolithography a resist mask 108 is formed on the protection insulating film 105 with an opening 107 on the designated area of the resist mask.
Next, as shown in FIG. 9B, the ILD is dry etched in reactive ion etching (RIE) utilizing the resist mask 108 for the etchingmask. Firstly, the protection insulating film 105 is etched in RIE by plasma excitation of CF4 gas. Secondly, the MSQ film 104 and the silicon oxide film 103 are etched in RIE by plasma excitation of the mixture of C4F8gas, N2gas, and Argon gas. Thus, a via 109 reaching the diffusion layer 102 is made out. In this process of dry etching, depending on RIE conditions, the surface of the resist mask 108 is heat affected by the impact of plasma ion and a modified layer 108a is formed there.
Subsequent process is removing the resist mask 108 including the modified layer 108a. As in FIG. 9C, active species of hydrogen is created by plasma exciting the mixed gas of hydrogen (H2) and inert gas (example: He, Ar) in a resist removing apparatus, and the resist mask 108 including the modified layer 108a is removed by irradiation of hydrogen atoms, which are derived from the hydrogen active species by excluding hydrogen molecular ion, or by irradiation of hydrogen radical III of hydrogen molecules. Resist removing above indicated is processed using a removing apparatus of which modeling illustration is given in FIG. 5, which shall be explained later. Time required for removing resist is one (1) to two (2) minutes including time for about 30% over etching. Time taken for resist removing varies depending on the thickness of a resist film, and over etching time varies according to the difference in level of front-end.
Consequently, as shown in FIG. 9D, the via 109, which reaches the diffusion layer 102 formed on the surface of the silicon substrate 101, is made through the multilayer of the ILD 106 consisting of the protection insulating film 105, the MSQ film 104, and the silicon oxide film 103. Then conductive material (via plug) is filled into the via 109, and the interconnect wiring layer is structured, though this specific part of the process is not illustrated in the drawing.